This 32G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 32Gbps within a single lane.32G Serdes including PCIe 5/4/3- Compatible with next generation PCIe standard protocol. Supporting various serial interface protocols within 32Gbps (PCIe5/Rapid IO/XAUI/SATA/fiber channel/10G Ethernet etc). The 32Gbps SERDES PHY is a low-power, area-optimized, silicon IP core designed to meet the power efficiency and performance requirements of applications for next-generation, high-speed wireline and wireless 5G infrastructure, artificial intelligence (AI), data center, edge, and graphics.
Compliant with PCIE, ATS, SR-IOv, CXS standards. Support for CCIX packets. Supports up to 32 Lanes. Available in End-Point/ Root-Complex/ Dual-Mode Switch configurations.
The USB PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with USB standard from Intel. 40/20/10/5 Gbps SuperSpeed+ speeds and HS and FS speeds are supported.
The Multi-SERDES PHY is a highly configurable design that supports SATA3, PCIe2 and XAUI with full compliance. High data rates are accurately achieved through fully programmable TX drivers and auto-calibrated on-die terminations. The design is completely self-contained including: I/O pads, primary and secondary ESD for simple integration and production testing is simplified through at-speed BIST, loopback and boundary scan.